Saturday, September 25, 2010

Building FPGA Communications Projects with LabVIEW

Summary: An introduction to developing digital communications and digital signal processing projects using LabVIEW's FPGA module. The purpose of this tutorial is to give users the foundation to build projects on FPGAs such as the NI-5640R IF-RIO.


The field-programmable array (FPGA) has emerged as a viable hardware implementation of digital signal processing functions. The primary advantage of an FPGA is its flexibility: FPGAs are reprogrammable through hardware description languages such as VHDL and Verilog HDL. In recent years, FPGAs have been closing the performance gap with non re-programmable application-specific integrated circuits (ASIC). Although the potential performance advantages of FPGAs are widely debated and beyond the scope of this report, we will mention here that some of the alleged performance advantages of FPGAs include improved I/O and parallel performance which afford higher rates of processing [2].

Purpose of this Tutorial

The purpose of this tutorial is to motivate you, the reader, to explore FPGA-based digital signal processing and communications projects using National Instrument’s (NI) LabVIEW. In this tutorial we use the NI PCI-5640 IF-RIO (intermediate frequency, reconfigurable input/output) transceiver, which contains the Virtex-II Pro FPGA. The technical specifications of the FPGA and transceiver can be found in NI PCI-5640R Specifications [4].
LabVIEW 8.6 contains an “FPGA module” that makes building and designing systems on the FPGA intuitive for the following reasons. You do not need to worry about writing hardware description languages, for the FPGA module synthesizes VHDL code for the FPGA during compilation. Instead, you will take advantage of LabVIEW’s graphical interface and inclusion of FPGA and DSP related modules make it convenient for developing a system with many components. Stated informally, with LabVIEW, you will be spending more time clicking and dragging rather than typing.

Overview: Developing an FPGA-Based Communications System in LabVIEW

The FPGA module in LabVIEW is capable of taking a VI file and synthesizing the HDL code when compiling the VI onto the FPGA. In this module, from the project explorer of an FPGA project, we can control countless processes and features on the FPGA such as multiple clocks, direct memory access (DMA), analog-to-digital (ADC) and digital-to-analog (DAC) converters, and memory blocks. Overall, FPGA application development can be broken down into two stages: development on the HOST VI and development on the FPGA VI.
The HOST VI controls the FPGA target from the computer. In addition to sending and acquiring values to and from the FPGA, it directs the execution of the program on the FPGA[5]. As seen in the HOST VI, the host begins by initializing the FPGA by configuring the DAC and ADC, and then specifying the size of the DMA buffers on the FPGA. In the context of a typical communications project, the HOST controls values such as carrier frequency, samples to acquire at the DAC and ADC, symbol rate, and loop gain coefficient at the Costas loop. PN generation, modulation, and transmission of the modulated signal on the channel occur continuously in a loop timed with the DAC clock on the FPGA.
The FPGA is programmed through the FPGA VI. Upon compilation, the FPGA module converts the VI block diagram to HDL code. Compilation times typically range from 10 to 40 minutes, depending on the complexity of the VI. Note that the HOST VI and its FPGA VI do not support the same VIs. You will find that various convenient signal processing and communications VIs are available on the HOST, including aModulation toolkit, and an assortment of filters, but not available on the FPGA. Furthermore, the FPGA can only support fixed, not floating-point operations. Thus, when developing on the FPGA it will be necessary to ensure that operations were being performed in fixed-point arithmetic.

Controlling the Sequence of Execution at the Host

As you have learned from the previous section, in LabVIEW, the Host controls the FPGA in software. How? Another logical question to ask is, “how do I control the execution of my program?” For example, in the context of a communications system, it is necessary to do certain things in sequence, such as bit-generation→ forward error correction coding → modulation → transmission.
We strongly recommend starting with the files, ni5640R Analog Input and Output (HOST).vi and ni5640R Analog Input and Output (FPGA).vi . These files should be available to you as FPGA-template files. These two files intuitively illustrate how the HOST and FPGA VI’s communicate. With these files, you will not need to build a communications system completely from scratch. Thus, these files will provide you with the building blocks in LabVIEW to build a communications system.
The HOST VI, in a nutshell, controls the execution of the FPGA. If you look at a typical HOST VI of a given FPGA-based system, you will almost always observe the sequence of the overall system as going from left to right, from one VI to another. A well-designed HOST VI will follow this convention.
A typical FPGA-based communications system on LabVIEW will start with by opening a reference to the FPGA via Open FPGA, highlighted below by the light blue square. This will ensure that the overall system functions a specific way by opening a bitfile (extension .lvbit) that is generated during compiling.
Figure 1
Open FPGA Reference VI
Open FPGA Reference VI (Picture 0.jpg)
As shown above, after Open FPGA, the next VIs (that have green on the top) that follow configure the analog to digital converter (ADC) and digital to analog converter (DAC), along with the ‘timebase’. Through these VIs, you have a ton of configurations of the IF-RIO transceiver at your disposal.
Note that it is up to you to dictate the program flow. It is in general, good practice, to configure the hardware early on in the sequence, as shown above.

Two Important VIs: Read/Write Control and Invoke Method

One essential VI that you will use at the HOST VI is the Read/Write Control.viwhich allows you to read and write controls from the Front Panel of the HOST to the FPGA. For example, you may want send certain values to the transmitter, such as carrier frequency or a seed value for pseudo-random number generation. Or you may want to toggle between various types of modulation (BPSK/QPSK/PAM) for this system. All of these functions depend on the Read/Write, which is denoted by an image of sunglasses and a pencil (as highlighted below by the green squares).
Note how Read/Write Control.vienables the HOST to control the FPGA.
Host VI Block Diagram:
Figure 2
Figure 2 (Picture 1.jpg)
At the FPGA VI:
Figure 3
Figure 3 (Picture 2.jpg)
The Read/Write Control.visends values (numerical, Boolean, etc) from the HOST to the FPGA. You may wonder, “how does the HOST tell the FPGA what to do?” You may also be curious as to how the HOST sends large quantities of data to the FPGA. The answer to both of these questions is the Invoke
The appearance of this VI is as follows. The name of the Method, such as “Transfer Processing”, or “Transfer AO” is surrounded by a pink background on the first row. On the second row, the type of method (read, write, start, halt, etc) is given. On the third row, ‘Element’ is used for receiving values to manipulate.
For large quantities of data, you will use Invoke Method.vito read and write data to and from the FPGA through the first in, first out (FIFO) direct memory access (DMA) buffers. Note that unlike Read/Write Control.viInvoke Method.vialso can be used on the FPGA VI. With Invoke, you can transfer data through FIFOs between the HOST and FPGA (target to host/host to target, denoted in red), and between different parts of the FPGA (target-scoped, denoted in orange).
Observe how for every ‘Read’ there is a ‘Write’ and vice-versa.
Understanding the previous VIs is essential to building a communications on the IF-RIO transceiver. Once again, the files, ni5640R Analog Input and Output (HOST).vi and ni5640R Analog Input and Output (FPGA).viwill already contain most of the settings and VIs you need to build a communications system. However, whenever you want to create a newRead/Write Control.vior Invoke, you can do so at the Project Explorer window.
Figure 4
Target-Scoped FIFOS (between Timed Loops on the FPGA)
Target-Scoped FIFOS (between Timed Loops on the FPGA) (Picture 3.jpg)
At the host, between the FPGA and the HOST
Figure 5
Figure 5 (Picture 4.jpg)

“Now, how do I build a Communications System on LabVIEW?”

We cannot emphasize enough the importance of keeping things simple when building a communications system in LabVIEW. Below is an actual approach that we took on in a previous FPGA-based communications project in LabVIEW:

Testing and Development of a Communications System (from [2])

Phase 1: Simulate the communications system without a channel in LabVIEW

“Since this was our first experience with LabVIEW, it was necessary to become acquainted with its general development environment. Our overall approach was to become familiar with software and then hardware basics (simple analog I/O on the transceiver) before ultimately implementing the communications system. Getting accustomed with programming in LabVIEW was straightforward and intuitive. In contrast, the FPGA is considerably more complex and therefore required a familiarity with the hardware and resulting limitations in software.
As our experience with programming in LabVIEW increased, we designed and simulated the components of the communication system in software separately. We did not begin to build a “true” communication system on the FPGA until we were able to successfully simulate the system (almost) entirely in software.”

Phase 2: Sending and receiving data across a channel

“Following simulation of the communications system entirely in software, the next step in the process was to familiarize ourselves with the I/O of the 5640R transceiver. Until completion of this stage, we were not interested in implementing any components of the communications system with an actual wireline channel. Our first task was to send and receive an analog signal on the same transceiver through DAC and ADC channel 0 on the FPGA. Fortunately, the FPGA module includes several example and template projects for handling I/O on the FPGA. One of these projects, “Analog Input and Output” proved to be the most useful for our purposes. In this example project, an analog signal is generated in software, sent to the FPGA for transmission, received, and then analyzed in software with plots of the signal’s power spectrum and I and Q channels. We started by modifying this project to generate basic signals such as a square wave. Furthermore, we explored the effects of the various controls on the FPGA, such as I and Q channel gain, number of samples to send and acquire, and center frequency.”

Phase 3: Simulate the communications system (in software) with a wireline channel

“Upon being able to send and receive simply modified signals via I/O on the transceiver, we implemented the communications system with an actual wireline channel—with very little taking place on the FPGA other than analog input and output. At the transmitter, PN generation and the actual BPSK modulation are executed in software in the HOST VI. Similarly, the Costas loop and DLL also take place in software in the HOST VI. First, samples of the BPSK modulated waveform written to the FPGA through a DMA buffer. Afterwards at the receiver, the outputs of the ADC in the FPGA are written to the HOST VI through another DMA buffer. These samples are then sent to the software-implemented Costas loop and DLL, at which the original bit sequence is recovered.”

Phase 4: Implement the transmitter on the FPGA

“The final phase of the project consisted of programming the FPGA to generate the PN sequence and modulate the signal. We began with a similar approach to that of phase 2 and focused our initial efforts towards sending a simple sinusoid at the FPGA. During this stage, we found that many of the original processing blocks at the FPGA VI originally found in NI’s example project were unnecessary for our purposes. Furthermore, we observed a sine-lookup table was necessary to transmit a sinusoid at the DAC in the FPGA. This was in stark contrast to our previous use of a shortcut VI called “sine wave generator” which turned out to be incompatible for use within timed loops in the FPGA VI. As mentioned above, timed loops are critical for operation on the FPGA. “
By taking a careful, step-by-step approach such as the one above, you will save yourself the headache of having to identify multiple errors and making multiple corrections all over the place. We have learned this the hard way over and over again."

A Communications System on the FPGA

Moving forward, we assume that you have at least some understanding of a communications system and its components, such as a phase locked loop (PLL), delay looked loop (DLL), the modulator, etc. We also assume that you have a basic grasp of digital signal processing (DSP) fundamentals.
LabVIEW itself contains various convenient DSP and communications VIs, such as a Modulation Toolkit and an assortment of filters that are tempting to use. While these will help during simulation, they unfortunately (as of the time of this tutorial) are not supported on the FPGA.
Figure 6
Tempting VIs Not Available on FPGA...yet.
Figure 7
Figure 8
Furthermore, the FPGA hardware can only support fixed, not floating-point operations. This is attributed to the limitations in hardware which necessitate fixed precision arithmetic. Thus, when developing on the FPGA VI, you will need to make sure that operations were being performed in fixed-point arithmetic.
It is also critical to understand how timed loops operate on the FPGA VI. For example, it may be tempting to use Sine Wave to quickly output sinusoids at the transmitter or receiver. However, this particular VI cannot be used within timed loops on the FPGA. For this reason, it is better to use lookup tables in which the frequency is determined by the amount in which the output of the lookup table increases in magnitude during each clock cycle.
In addition, it is important to configure the ADC and DAC properly. For example, when the DAC is configured at the HOST to be in ‘Quadrature Mode’, it automatically interleaves outputs between in-phase (I) and quadrature (Q - the 90 degree phase shift is automatically performed by the DAC) modes. In other words, the in-phase component of the analog output is transmitted every other clock cycle.

Putting It Together: An Example of a BPSK Transmitter

The following block diagrams show the construction of a binary phase-shift keying (BPSK) modulator at the transmitter with these constraints in mind.
Note how a mod-16384 counter is used for the sine lookup table. We use a mod-16384 counter because 16384 is the length of the sine lookup table. When two values in the shift register are not equal, a 180 degree phase shift is induced by adding 8192 (half the length of the lookup table) to the counter such that the outputs of the sine lookup table are now shifted by a phase of 180 degrees, performing BPSK modulation.
A step-by-step instruction on how to build a BPSK system along with the working code can be found at (website). More examples can be found at the appendix
Figure 9
The transmitter in software at the HOST
The transmitter in software at the HOST  (Picture 5.jpg)

Some Ideas for Other Communications Projects

Hopefully, this tutorial has given you the motivation and basis to explore more efficient and widely adopted modulation schemes such as differential BPSK, quadrature amplitude modulation (QAM), and quadrature phase-shift keying (QPSK). There are many examples of these FPGA-based implementations in LabVIEW out there on the internet at . The features of the 5640R IF-RIO Transceiver and LabVIEW are conducive to such ideas. For example, the ability to configure the DAC on the 5640R to ‘Quadrature Mode’ and quickly build lookup tables in LabVIEW may help you build a QPSK system.
It will be up to you to determine what components of the communications system to place in hardware, on the FPGA, and in software, at the HOST. A potentially more optimal, realistic, and complex system would incorporate all components into the FPGA.
A particularly useful tutorial on Connexions by Ed Doering [4] presents many interesting digital communications projects on LabVIEW that incorporate noise and error-correction coding. We challenge you to implement these communications systems on the FPGA. Moreover, if you would like to learn more on why FPGAs are of interest for communications engineers, [6] is a highly-recommended resource that is extensive in content and concisely written.


[1] M. Parker, “FPGA versus DSP design reliability and maintenance”
[2] C. Li, A. Muehlfeld, “ECE 420 Final Project: An FPGA-Based Communications System on LabVIEW”
[3] National Instruments, “Getting Started with the NI PCI-5640R IF Transceiver and the LabVIEW FPGA Module”
[4] E. Doering, “Communication Systems Projects with LabVIEW”
[5] National Instruments, “NI PCI-5640R Specifications: Reconfigurable IF Transceiver”
[6] C. Dick, M. Rice, and F. Harris, “Configurable logic for wireless communications: carrier and symbol synchronization”

Appendix – Some More Examples

PN Generation and BPSK Modulation on the FPGA
The following diagram is the VI that generated the PN sequence and performed BPSK modulation. This VI was compiled into VHDL, synthesized, and mapped onto the FPGA. The top half of the VI handles BPSK modulation, and input to the DAC. The bottom half of the VI handles the PN generation, which is input to the BPSK modulator.


Costas Loop in Software
The following diagram shows the VI implementing a Costas loop to track the modulation carrier frequency. The two blue blocks near the center are the numerically controlled sine and cosine oscillators. Toward the right are the two low pass filters which output I and Q values, as well as the sign extractor which distinguishes the Costas loop from a phase locked loop.


Delay Locked Loop in Software
The following diagram shows the VI implementing a delay locked loop, used to track the optimal cycle for sampling bits. Toward the left is the shift register and summation implementing the matched filter. In the center is the logic for deciding which sample is the optimal sample and for adjusting the counter accordingly.

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